Power Optimization for On-Chip Communication architectures in MPSoC
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| Title | Power Optimization for On-Chip Communication architectures in MPSoC |
| Authors | |
| Abstract | As multi-processor computer systems become more prevalent in today’s computer industry, it is clear that routers and interconnection networks are critical components of these multi-processor systems. Therefore, there is a need to obtain accurate area and power models for these critical components so that we can better understand the area and power tradeoffs as we balance the on-chip and off-chip communication energy given a fixed energy budget. We shows that multiplexer routers are more area and power efficient compared to matrix routers since matrix routers quickly exhibit a quadratic-like increase in area and power as the number of ports and port width increases. In addition, we show that there is a real gain in area when the router is shared among 4 or more cores. The savings by sharing the same router among multiple cores does not continue indefinitely, since after a certain port number and port width size, the increase in the crossbar size can no longer be compensated by sharing the router. |
| Publisher | World Science Publisher |
| Date | 2012-04-12 |
| Source | 2167-6372 |
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