Hardening FPGA-based Systems Against SEUs: A New Design Methodology
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| Title | Hardening FPGA-based Systems Against SEUs: A New Design Methodology |
| Authors | |
| Abstract | SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarkscircuits and on a realistic circuit to show the capabilities of the proposed design flow. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2006-04-01 |
| Source | Journal of Computers Vol 1, No 1 (2006) |
| Rights | Copyright © ACADEMY PUBLISHER - All Rights Reserved.To request permission, please check out URL: http://www.academypublisher.com/copyrightpermission.html. |