Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs
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| Title | Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs |
| Authors | |
| Abstract | Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding the optimal number of sleep transistors and their placement as well as optimal P/G network grids, wire widths and layers. This paper presents a fake via based sleep transistor P/G network synthesis method, which addresses the requirements from industrial power-gating designs. The method produces optimal sleep transistor P/G networks by simultaneously optimizing sleep transistor insertion and placement as well as the power network grids and wires for minimum area, maximum routability with a given IR-drop target. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2008-03-01 |
| Source | Journal of Computers Vol 3, No 3 (2008) |
| Rights | Copyright © ACADEMY PUBLISHER - All Rights Reserved.To request permission, please check out URL: http://www.academypublisher.com/copyrightpermission.html. |