Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design
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| Title | Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design |
| Authors | |
| Abstract | The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work focuses on low-power consumption to achieve longer life-time of batteries. A 2.4GHz frequency synthesizer has been fabricated in 0.18µm epi-digital CMOS technology for ZigBee applications, which consumed 7.95 mW from 1.8V supply. The synthesizer has achieved phase-noise of −81.55dBc/Hz and −108. 55dBc/Hz at 100kHz and 1MHz offset, respectively. The settling time measured is less than 25µs for an output frequency change of 75MHz from 2.4GHz. The chip core area is 0.75 × 0.65mm2. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2008-04-01 |
| Source | Journal of Computers Vol 3, No 4 (2008) |
| Rights | Copyright © ACADEMY PUBLISHER - All Rights Reserved.To request permission, please check out URL: http://www.academypublisher.com/copyrightpermission.html. |