Fast Algorithm of A 64-bit Decimal Logarithmic Converter
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| Title | Fast Algorithm of A 64-bit Decimal Logarithmic Converter |
| Authors | |
| Abstract | The paper presents an efficient algorithm to compute base-10 logarithm of a decimal number. The algorithm uses a 64-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations. It is the first FPGA prototype of its kind that uses a 64-bit (decimal 16-digit) precision. Two numerical examples have been presented for the purpose of illustration. The algorithm produces very accurate result with a maximum absolute error of 3.53x10-14. The architecture is pipelined and implemented on to the Xilinx Virtex2p FPGA. It costs 6,752 logic cells, outputs at a minimum rate of 51 mega-samples/sec, and consumes 125.7 mW of power. The scheme is very suitable for timing and accuracy critical applications and compliant with the IEEE754-2008 standard (decimal64 format). |
| Publisher | ACADEMY PUBLISHER |
| Date | 2010-12-01 |
| Source | Journal of Computers Vol 5, No 12 (2010): Special Issue: Selected Papers of the IEEE International Conference on Compute |
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