Guest Editorial
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| Title | Guest Editorial |
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| Abstract | The multi-disciplinary approach to engineering has become an important factor for the design of many new products, systems and processes. The systems integration of engineering areas in circuits, electronics, controls, signals and computing exploits and exceeds the relative advantages of single disciplines.This special issue comprises of six selected papers from the 2nd International Conference on Signals, Circuits and Systems (SCS 2008), Hammamet, Tunisia, 7-9 November 2008. The aim of the 2008 International conference on Signals, Circuits & Systems (SCS’08) is to cope with the rapidly progressing technology. The multi-disciplinary approach to engineering has become the key to many different products and processes. The integration of mechanics, electronics, control and computing exploits and exceeds the relative advantages of single disciplines, and when they are integrated, the synergy ensures that performances reach unprecedented levels. The conference was sponsored by IEEE Signal Processing Society, IEEE Circuits and Systems Society and Association Université et Environnement, and organized by National Engineering School of Sfax (ENIS) and Electronics, Microtechnology & Communication Laboratory (EMC). The proceedings of the SCS 2008 were included in IEEE Xplore.The conference received more than 177 paper submissions from 34 countries and regions, of which 67 were selected for oral presentation and 33 papers as posters. From these research papers, through two rounds of reviewing, the guest editor selected six as the best papers of the Conference. In “Analysis of Chaos-Based Coded Modulations under Intersymbol Interference”, Francisco J. Escribano, Luis López, and Miguel A. F. Sanjuán analyze the behavior of a class of chaos-based coded modulations (CCM’s) in channels with time-invariant intersymbol interference (ISI). The authors use the ISI distance spectrum of the CCM’s to calculte bounds for the bit error rate (BER), and provide the analytical condition a CCM has to comply to stand a limited quantity of ISI. The effect of the main modelling parameter of this class of chaos-based systems was explained, and it was shown that the dynamics of the underlying chaotic map is in each case the main factor to account for the final performance. The results show that CCM systems are of potential interest in this kind of distorting environment.In “Extraction and Simulation of Intra-gate Defects Affecting CMOS Libraries”, Aymen Ladhar and Mohamed Masmoudi present an automated approach to extract and simulate potential intragate defects in standard cell library, based on the use of verification and simulation CAD tools. As application, the authors used these fault signatures to diagnose different types of intra-gate defects. Experimental results show the efficiency of the approach to isolate injected defects on industrial designs.In “Pseudorandom Direct Sampler for Non-Uniform Sub-sampling Architecture in a Multistandard Receiver”, Asma Maalej, Manel Ben-Romdhane, Chiheb Rebai, Patricia Desgreys, Patrick Loumeau, and Adel Ghazel propose a Non-Uniform Sampling (NUS) technique for down-conversion stage in a multistandard radio. For both narrowband and wideband standard processing, NUS promises relaxing system design constraints, decreasing the sampling frequency as well as reducing power consumption. A non-uniform clock generator, called Pseudorandom Direct Sampler (PDS), is described. PDS is used to non-uniformly control the Analog-to-Digital Converter (ADC) performing IF sub-sampling in proposed GSM/UMTS/WiFi multistandard receiver architecture. PDS architecture is based on using modified Direct Digital Synthesizer (DDS) including pseudorandom behavior. A 90-nm CMOS FPGA based prototype of PDS reveals an internal clocking up to 350 MHz and a power consumption lower than 4 mW.In “On Digital Filtering of Band-limited Signals Using Lower Sampling Rates”, Kostadin Tzvetkov and Andrzej Tarczynski explore filtering of multi-band bandlimited signals by means of a linear digital filter with one or more stopbands. The main goal of the paper is to demonstrate that such a task can be accomplished using sampling rates lower than Landau rate, where the Landau rate is defined as the total bandwidth of the input signal. In order to reach such low rates Periodic Nonuniform Sampling is employed. The authors show that the proposed filtering method is most efficient when bandpass and multiband filtering is required. Necessary and sufficient conditions for filtering are derived, and an algorithm for designing PNS grids that allow sub-Landau sampling and filtering is proposed. Reconstruction systems are discussed and experimental examples are presented, which confirm the feasibility of the approach.In “Digital High Order Multiplier-free Delta Sigma Modulator for Multistandard Fractional-N Frequency Synthesizer”, Manel Ben-Romdhane, Aymen Abeda, and Chiheb Rebai propose a new stable design strategy for 1-bit high order digital DS modulator for multistandard fractional-N frequency synthesizer. The proposed digital DS modulator presents simplicity, low power consumption and controls a dualmodulus divider instead of multi-modulus one as in existing DS fractional-N frequency synthesizer. Simulation results illustrate the DS modulator good performances in terms of spectrum purity and accuracy. Using this stable 1-bit digital DS modulator output to a fractional-N frequency synthesizer Simulink model verifies the multistandard frequency synthesizer specifications.In “Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-2m Array Multipliers”, Leandro Z. Pieper, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Sergio Bampi, and José C. Monteiro introduce new dedicated blocks for radix-2m multiplication. These blocks are basic components of the structure of the 2´s complement radix-2m array multiplier previously proposed in the literature. In the original array multiplier, the blocks that perform the radix-2m multiplication were automatically synthesized from a truth table. The dedicated multiplication blocks the authors propose are themselves composed of a structure of less complex multiplication blocks and resort to efficient Carry Save adders (CSA). This new scheme can be naturally extended for different radices multiplication. The paper presents results of area, delay and power consumption for 16, 32 and 64 bit array multipliers using the new dedicated modules. The results show that by using the new dedicated modules, the array multipliers are more efficient in terms of delay and power consumption when compared both against the original array structure and the Modified Booth multiplier.We would like to take this opportunity to thank the authors for the efforts they put in the preparation of the manuscripts and for their valuable contributions. We wish to express our deepest gratitude to the program committee members for their help in selecting papers for this issue and especially the referees of the extended versions of the selected papers for their thorough reviews under a tight time schedule. Last, but not least, our thanks go to the Editorial Board of the Journal of Computers for the exceptional effort they did throughout this process. In closing, we sincerely hope that you will enjoy reading this special issue. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2010-10-01 |
| Source | Journal of Computers Vol 5, No 10 (2010): Special Issue: Selected Papers of The Second International Conference on Signa |
| Rights | Copyright © ACADEMY PUBLISHER - All Rights Reserved.To request permission, please check out URL: http://www.academypublisher.com/copyrightpermission.html. |