A Modified Technique for Analysis of Synchronous Counters Constructed with Flip-flops
|
| Title | A Modified Technique for Analysis of Synchronous Counters Constructed with Flip-flops |
| Authors | |
| Abstract | Some methods of fabrication make it economically attractive to construct counters (and other devices) by connecting sets of identical flip-flops(FFs), if the FFs have a common clock input, the state transitions of the whole counters are as rapid as the state transitions of each FFs, so that the counter is further restricted to be synchronous. In order to simplify the process for analysis of synchronous counters constructed with flip-flops, a simple and successful method is proposed. Using this method, the state transition equations obtained from logic diagram of counter are converted to standard sum-of-products forms(SOPs). By finding out the logic principle for achieving the value of logic function based on the standard SOPs, the values of next state can be directly obtained without any Boolean calculation. Analysis for a 3-bits counter shows that this method eliminates complex calculations， and makes the process of obtaining next state value and developing truth table more rapid and convenient. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2011-08-01 |
| Source | Journal of Computers Vol 6, No 9 (2011): Special Issue: Changes in Computer Application for Economic Analysis of Law and |
| Rights | Copyright © ACADEMY PUBLISHER - All Rights Reserved.To request permission, please check out URL: http://www.academypublisher.com/copyrightpermission.html. |