A Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems
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| Title | A Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems |
| Authors | |
| Abstract | Recent system design trends suggest multicore architecture for all computing platforms including distributed and embedded systems running real-time applications. Multilevel caches in a multicore system pose serious challenges as cache requires huge amount of energy to be operated and cache increases unpredictability due to its dynamic behavior. Bandwidth and synchronization problems are also critical design factors for distributed and embedded systems. In this work, we propose a “miss table” based cache memory organization which is very effective for real-time distributed and embedded systems. Cache-level miss table holds information about the memory blocks that cause most level-1 cache (CL1) misses under normal execution. Proposed cache organization also includes private victim caches (VCs) to hold level-1 victim blocks and shared level-2 cache (CL2) to help synchronization. Proposed cache organization improves CL1 cache hits that decrease memory latency and total power consumption and improve predictability and bandwidth. We simulate an 4-core system with two-level caches using MPEG4, H.264/AVC, FFT, MI, and DFT workload. Experimental results show that the proposed miss table based cache organization helps reduce average memory latency and total power consumption by 31% and 38%, respectively, when compared with cache organization without miss table and victim caches. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2013-01-01 |
| Source | Journal of Computers Vol 8, No 1 (2013): Special Issue: Parallel Architecture, Algorithms and Programming |
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