FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm
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| Title | FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm |
| Authors | |
| Abstract | In this paper, a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN – IEEE 802.11n) standard. The results show that theproposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms. The proposed algorithm has been implemented and tested on Xilinx Virtex 5 FPGA. With significantly reduced hardware resources, the implemented decoder can achieve an average throughput of ~16.2 Gbps with a BER performance of 10-5 at an Eb/No of 6.25 dB. |
| Publisher | ACADEMY PUBLISHER |
| Date | 2011-01-01 |
| Source | Journal of Networks Vol 6, No 1 (2011): Special Issue: Selected Papers of the IEEE International Conference on Computer |
| Rights | Copyright © ACADEMY PUBLISHER - All Rights Reserved.To request permission, please check out URL: http://www.academypublisher.com/copyrightpermission.html. |